Tanner-Tools- v15

Tanner Tools Version 15.00

What’s New in S-Edit v15.00

Spice and Verilog-A Text Views
S-Edit now supports Spice and Verilog-A text views. Any combination of i) schematic,
ii) Spice, and iii) Verilog-A view may be saved for a cell. The view that is used when
simulating is given by a priority list of view types and view names defined in the
Hierarchy Priority tab of the Setup Simulation dialog. A similar list is on the Export
Spice dialog for use when exporting Spice.

Spice Command Tool
The Spice Command Tool for inserting new Spice commands is now available in the
Additional Spice Commands page of the Setup Simulation dialog. The Insert
Command… button is used to invoke the wizard.

Model Parameter Listings
A table showing all the models supported in T-Spice is now available in S-Edit via the
Help > Models Supported by T-Spice… menu. A table showing the models used in
the libraries specified for the current design is available via Tools > T-Spice Library
Models, and a table showing the device parameters for all devices in the design is
available via Tools > T-Spice Device Parameters… . The Help > Models Supported
by T-Spice table shows default values for all models and devices, whereas the Tools
menu shows tables with the actual models and device values to be used in the
simulation of the current design.

Design Checks
Performance of design checks has been significantly improved. A limit of 20 errors
are reported for each design rule.
A new design check for checking overlapping wires has been added.
The default severity of “illegal connectivity” design checks, such as connecting buses
of different widths, is now Error instead of Warning.
The design check for overlapping instances now ignores symbols that do not have
any ports. This prevents the design check from flagging frame instances, which
overlap the entire schematic.
Design check now performs cell name checks in a case insensitive manner. Cell
names in different libraries with same name but different case will now issue a
warning/error.

Bug Fixes
Performance of Push and Pop context is significantly improved.
Design checks now properly identifies the case when two cells with same name are
instanced from different libraries.
Fixed problem when importing an EDIF schematic file created in S-Edit, the option
“Overwrite existing views” did not work properly.
S-Edit has a new Simulation Setup option, “Keep all simulation results”. When True,
a time stamp is appended to the Simulation Results folder, so each simulation is
saved in a unique folder. When False, prior results are overwritten.

2

Fixed problem where Verilog import would have missing pins when a module
definition contains a port, but does not declare the port in the module’s contents.
These ports will now be declared as type “other” and a warning will be issued.
Verilog import now imports parameters.
Ports containing buses with {} brackets now import properly.
Verilog Import dialog no longer reverts the TieHigh cell: value to TieHigh even when
something else is specified.
Fixed a problem where Property set would apply to selections that were not on the
active page.
Selecting properties on symbols will now select the property that is clicked on. Using
the left mouse button will cycle through overlapping properties, allowing one to select
difficult to select properties.
Fixed a problem where a box width could not be changed to be greater than 66
inches.
An option “Exclude simulator commands” is added to the Spice Export dialog to
suppress simulation setup commands during Spice export.
“New properties ${PageNumber} and ${Pages} have been added. ${PageNumber}
evaluates to the 1-based index of the page that contains the instance. ${Pages}
evaluates to the total number of pages in the schematic view that contains the
instance.
Zoom to selection now works correctly on highlighted nets
ORCAD EDIF files may now be imported and the netlisting commands are correctly
translated for exporting Spice.
“Author (renamed from “Creator”), Version, Modification Date (“Last Modified”), Info
and Organization and RevisionCount are now included as column choices in the
View Navigator.
Import of Cadence EDIF files now reads callbacks from the cdf file and places the
function name and parameters on the property. A tcl file with stubs for the functions is
created for the user to provide the content of the tcl function.
Problems importing EDIF written by the Gateway Schematic Editor are fixed.
Tcl scripts saved from S-Edit and placed in the user preferences startup folder wll
now properly load on program startup.
Exported netlists are now sorted within each sort order block. The sort first sorts the
alphabetic characters and then sorts any numbers in the name as a number. For
example, the sort will produce C1, C2, C10, C11, wheras a normal alphabetical sort
would be C1, C10, C11, C2.
Printing will now print all pages of a schematic view, rather than just the first.
In Setup SPICE Simulation, the Verilog search path is now saved.
When separated by a space instead of a comma, negative values in temperature
sweeps were being evaluated as an expression. The description field has been
enhanced with: “Use commas to separate negative numbers or expressions”
Annotations on schematic are now updated automatically after each simulation. It is
no longer required to turn off then back on annotations to update after a simulation.
The InstanceName property on a symbol can now be used as a prefix to use for the
instance name when creating a new instance. If InstanceName is “M” then instances
will be named M_1, M_2, etc. If InstanceName is blank, then the cell name is used.