Software training,tutorials,download,torrentEarly Design Analysis Tools Enable Efficient Verification and Optimization of SoC Designs
Using many advanced algorithms and analysis techniques, the SpyGlass® platform provides designers with insight about their design, early in the process at RTL. It functions like an interactive guidance system for design engineers and managers, finding the fastest and least expensive path to implementation for complex SoCs.
Early Design Analysis for Logic Designers
Inefficiencies during RTL design usually surface as critical design bugs during the late stages of design implementation. If detected, these bugs will often lead to iterations, and if left undetected, they will lead to silicon re-spins. The SpyGlass® product family is the industry standard for early design analysis with the most in-depth analysis at the RTL design phase. SpyGlass provides an integrated solution for analysis, debug and fixing with a comprehensive set of capabilities for structural and electrical issues all tied to the RTL description of design.
SpyGlass CDC
Comprehensive, Low-Noise Clock Domain Crossing Verification
Among the many verification challenges confronting system-on-chip (SoC) designers today, clock domain crossings (CDC) ranks near the top in difficulty. Today’s SoCs have dozens or sometimes even hundreds of asynchronous clock domains, making it very difficult to verify using conventional simulation or static timing analysis (STA). RTL simulation is not designed to verify metastability effects which cause data transfer issues across asynchronous clock boundaries and STA does not address asynchronous clock domains issues.
SpyGlass for FPGA Designs
Asynchronous Clock Domain Crossing Analysis
Among the many verification challenges confronting FPGA designers, clock domain crossings (CDC) ranks near the top in difficulty. Today’s designs have dozens of asynchronous clock domains, making it difficult to verify using conventional simulation or static timing analysis (STA). The SpyGlass® product family is the industry standard for early design analysis with the most in-depth analysis at the RTL design phase. SpyGlass provides an integrated solution for analysis, debug and fixing with a comprehensive set of capabilities for structural and electrical issues all tied to the RTL description of design.
Product: Synopsys Spyglass 2019.06 SP1
Version: 2019.06
Supported Architectures: x64/Linux
Language: english
Supported Operating Systems: Linux OS
Size: 1DVD