Mentor-Graphics-PADS-2007.4

Complete PCB design solution combining schematic definition with powerful layout and simulation tools
Integrated design environment combines ease of use with functional depth
With PADS PCB design solutions, you will:
Achieve a high ROI on PCB designs ranging from basic to complex
Improve productivity with shorter design cycles
Maintain design integrity with the latest analysis and simulation tools
High-speed routing improvements: controls for matched length nets and differential routing improvements.
Square and chamfered corners, DXF-in import, and via matrixing enhancements for RF design.
Blind/buried via drill table improvements: designs with partial vias (blind or buried) are automatically updated with the layer pairs and drill count of the partial vias in the design.
Alpha-numeric pin improvements: simplifies creation of large BGA-based parts.
ECO enhancements: includes comparison of design rules between the schematic and layout databases.
Design for fabrication (DFF) analysis: powerful fabrication checks, such as acid trap, starved thermals, solder mask slivers are checked in the CAD environment and database, allowing the designer to identify and correct manufacturing problems in PADS Layout, before Gerber generation.
Pin number visibility: the user has the ability to turn on/off the visibility of the component pin numbers, either numeric or alpha-numeric, improving designer productivity during routing.
SI analysis: integration of DxDesigner(TM) and the HyperLynx(R) LineSim(R) tool through a new interface allows fast transfer of a circuit for analysis and back annotation of termination resistor values.
Analog simulation: provides a board level simulation analysis and verification through a common schematic editor for both simulation and PCB design entry
“Mentor Graphics has demonstrated exceptional productivity benefits in optimizing the FPGA-to-PCB integration process with I/O Designer,” said Danny Biran, Altera’s senior vice president of product and corporate marketing. “The introduction of I/O Designer for PADS will bring the benefits of cycle time reduction and lower PCB costs to a broader FPGA / PCB customer base. Altera’s advanced FPGA technology, combined with I/O Designer for PADS, is a perfect solution for the PADS user to expand their mainstream FPGA usage.”

The PADS I/O Designer Product
The PADS I/O Designer family provides for concurrent design of the FPGA and PCB by bridging these unique design flows and automating the various processes needed to implement today’s high pin-count, high-speed FPGAs on PCBs. Starting with nothing or an early hardware design language (HDL) description or a top-level DxDesigner(TM) product, the FPGA-PCB interface is quickly defined with a variety of correct by construction, drag and drop PCB signal to FPGA pin assignment methods. The PADS I/O Designer product then synchronizes the interface across the FPGA and PCB flows through:

Automatic DxDesigner and schematic generation
Automatic generation & maintenance of required FPGA vendor files, HDL files, and synthesis constraint files
Optionally, the PADS I/O Designer product will import the PADS Layout physical design for FPGA vendor rules-driven pin swaps. When extended to PCB optimization, the PADS I/O Designer product leverages the PADS Layout physical design to drive PCB trace optimization through FPGA interface unraveling. Also available is functionality to optimize multiple FPGA interfaces simultaneously within a single PADS Layout physical design.