Software training,tutorials,download,torrentLaker Custom Layout System
The Laker™ Custom Layout System offers powerful solutions for analog, mixed-signal, memory, and custom digital IC design that address key pain points in the layout process. The Laker layout system provides an intuitive methodology and controllable automation that let you quickly achieve superior layout results. The Laker layout system helps you:
Simplify your job by automating manytedious and error-prone layout tasks;
Maximize your layout skills using advanced automation that you control;
Minimize your CAD support requirements; and
Reduce your overall cost of design.
Superior Layout with Less Effort
Hundreds of companies have deployed the Laker Custom Layout System in their design flows to produce high-quality, high-density layout of advanced chip designs. Laker automation technologies reduce the effort required to obtain optimal layout by helping you:
Speed up your project and optimize your layout at the same time;
Efficiently interact with your netlist, schematic and layout data in a single working environment;
Cut overall DRC/LVS run times by creating layout that is correct the first time; and
Reduce or eliminate PCell scripting with unique device generation technologies.
The Laker Custom Layout system uses unique technologies to exploit design rules, connectivity and parameters during layout in an efficient, consistent, and automatic way. The system’s schematic-driven layout (SDL) capabilities save you time so you can focus on creating the best possible layout. By handling dozens of critical requirements in an automated yet natural way, the Laker layout system keeps you in complete control of the quality of your results.
Schematic-driven layout: You are able to rapidly create optimized layout that is DRC/LVS-correct in less time without sacrificing density or design styles. Both netlist and schematic views are included with the world-class Laker layout editor for an intuitive SDL working environment, which includes:
Hierarchical design browser allows you to rapidly search the hierarchy and cross probe between schematic, netlist, and layout. Modify the design hierarchy for more efficient layout by flattening logical groups of devices into higher level devices
Schematic view enables schematic-driven layout. Cross-probe with design browser to identify candidates for flattening. Automatically identify repeated patterns, associate optimized layout for those patterns and generate layout in seconds
Layout editor enables rapid, rule-driven layout. Realize, place, route, and edit physical layout that is DRC- and LVS-correct
Patented automatic schematic generator creates a readable schematic from EDIF, Verilog®, CDL or SPICE netlists
Stick Diagram Compiler: Based on SpringSoft’s unique MCell technology, the Stick Diagram Compiler executes transistor floor-planning on-the-fly during device generation in the SDL flow. View and optimize device layout at a higher level of abstraction: swap, merge, move, spilt and align gates at a symbolic level without having to worry about design rules, connectivity or parameter values.
Built-in Automatic Transistor Placer offers a multi-row placement capability for PMOS and NMOS transistors that displays the best transistor placement for area and routing based on your given placement criteria