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Cadence-ASSURA- V3.17 for Linux


Assura™ Design Rule Checker (DRC) is part of the design verification suite of tools within the Virtuoso® custom design platform. Assura DRC is a full-featured tool that supports both interactive and batch operation modes and utilizes hierarchical processing for fast, efficient identification and correction of design rule errors in even the most advanced designs.

Key benefits

Simplifies design process with a common database for data transfer within the Virtuoso custom design platform
Accelerates design-to-volume with production-proven interactive design rule checking
Reduces re-spins by eliminating design rule errors before tapeout
Ensures fast, silicon-accurate custom design with an integrated silicon verification and analysis flow within the Virtuoso custom design platform

Assura™ Layout vs. Schematic (LVS) Verifier is part of the design verification suite of tools within the Virtuoso® custom design platform. Assura LVS ensures that the layout connectivity of the physical design matches the logical design represented by the schematic or netlist before tapeout by automatically extracting devices and nets formed across layout hierarchy and comparing them to the schematic netlist. Assura LVS provides fast, efficient verification in both interactive and batch mode.

Key benefits

Simplifies design process with a common database for data transfer within the Virtuoso custom design platform
Accelerates design-to-volume with production-proven interactive LVS debugger
Reduces re-spins by eliminating connectivity and mismatch errors before tapeout
Ensures success in analog mixed-signal design with support of mixed netlist and special devices