Siemens Catapult High-Level Synthesis 2025

Siemens Catapult HLS Overview

Siemens Catapult High-Level Synthesis (HLS) is a leading electronic design automation (EDA) tool suite developed by Siemens EDA (formerly Mentor Graphics). It enables hardware designers to create register-transfer level (RTL) implementations for ASICs and FPGAs directly from high-level languages like C++ and SystemC, significantly accelerating the design and verification process. This approach reduces coding effort by up to 80% compared to traditional RTL hand-coding and boosts simulation speeds by up to 1,000x.

Key benefits include:

• Faster Time-to-Market: Shortens the overall design and verification flow by addressing increasing complexity in chip design.
• Quality of Results (QoR): Delivers optimized RTL for performance, power, and area (PPA), with features like physically aware multi-VT optimization and ASIC power estimation.
• Verification Efficiency: Integrates high-level verification (HLV) tools for functional checking, code coverage, and formal analysis, potentially reducing SoC verification costs by up to 80%.
• AI/ML Support: Specialized Catapult AI NN extensions allow translation of Python-based neural network models into efficient hardware accelerators, ideal for edge computing and inferencing.

The platform supports a comprehensive flow from high-level design input to targeted implementations for ASICs, eFPGAs, or FPGAs, with independence from specific hardware targets.

What’s New or Relevant for 2025?

While Catapult HLS is continuously updated, 2025 highlights include:

• Internship Program: Siemens is recruiting for a “Strategic Student Program: Catapult HLS AI Intern” focused on AI enhancements, running through Summer 2025. This role involves developing AI inferencing accelerators using HLS methodologies.
• HLS Academy Challenge: A free online learning resource and forum from Siemens HLS Academy features a low-power AI/ML inference challenge running from July 2 to October 31, 2025. It emphasizes energy-efficient designs for battery-powered or energy-harvested edge devices.
• Ongoing Events and Training: Siemens continues to host hands-on workshops and sessions at conferences like DAC and Embedded World, covering HLS best practices for ML, image processing, and RISC-V integration. On-demand training paths are available for C++/SystemC design, debug, and verification using libraries like MatchLib.

Product:Siemens Catapult High-Level Synthesis 2025
Version: 2025
Supported Architectures: x64
Language: english
Supported Operating Systems: Windows 10even or newer/Linux
Size: 1DVD