SpyGlass Lint

Early Design Analysis for Logic Designers

Inefficiencies during RTL design usually surface as critical design bugs during the late stages of design implementation. If detected, these bugs will often lead to iterations, and if left undetected, they will lead to silicon re-spins. The SpyGlass® product family is the industry standard for early design analysis with the most in-depth analysis at the RTL design phase. SpyGlass provides an integrated solution for analysis, debug and fixing with a comprehensive set of capabilities for structural and electrical issues all tied to the RTL description of design.

SpyGlass CDC

Comprehensive, Low-Noise Clock Domain Crossing Verification

Among the many verification challenges confronting system-on-chip (SoC) designers today, clock domain crossings (CDC) ranks near the top in difficulty. Today’s SoCs have dozens or sometimes even hundreds of asynchronous clock domains, making it very difficult to verify using conventional simulation or static timing analysis (STA). RTL simulation is not designed to verify metastability effects which cause data transfer issues across asynchronous clock boundaries and STA does not address asynchronous clock domains issues.

SpyGlass RDC

Comprehensive, Low-Noise Reset Analysis

Clock domain crossings (CDCs) are a well-known source of metastability. However, they are not the only source. Asynchronous reset crossings within a same clock domain can also cause metastability. Use of asynchronous resets is becoming more prevalent because of the wider use of multiphase power-up boot sequences. As a consequence, Reset Domain Crossing (RDC) issues are causing more and more design errors. Such errors can add significant time and expense to the design and debug cycles, and may even find their way into the silicon, necessitating costly respins. Like CDC verification, RDC verification is equally important to ensure that the designs work as expected. For both of these, you need a high-powered, comprehensive solution

Product:Synopsys SpyGlass vn2018 for Linux
Version: 2018_v15.0
Supported Architectures: x64
Language: english
Supported Operating Systems: Linux/ RHEL 6.X、CentOS 6.X
Size: 1DVD

Synopsys SpyGlass 2018 for Linux

SpyGlass Lint

Early Design Analysis for Logic Designers

SpyGlass CDC

Comprehensive, Low-Noise Clock Domain Crossing Verification

SpyGlass RDC

Comprehensive, Low-Noise Reset Analysis

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