Using advanced static and dynamic analysis, the SpyGlass® solution pinpoints structural, coding and consistency problems at RTL. In addition, the solution offers the industy's most comprehensive solution for analysis of clock, reset and clock domain crossings (CDC). It traces problems to their source, helps users resolve issues before they creep into downstream design implementation. The SpyGlass solution also helps address electrical rules (ERC) in the design.

Slashing the Risk of Complex IC Development
The SpyGlass solution greatly reduces the risk of developing complex multimillion-gate, nanometer-scale ICs, enabling companies to build better products, faster and more economically. The SpyGlass solution accurately detects design issues at the point of creation. In traditional flows, such problems are typically discovered much later, at the gate level, if at all, after much time and expense have been invested in the design. With the SpyGlass solution, designers can optimize designs at RTL, when the ability to make enhancements is greatest and the cost of modifications lowest. And the SpyGlass solution flags areas of the design that are likely to present implementation challenges, so that appropriate resources can be applied to mitigate schedule and complexity risk.

In detecting problems and helping effect their resolution, the SpyGlass solution leverages decades of accumulated design experience. It integrates a large base of industry-standard best practices, as well as Atrenta's own extensive experience working with industry-leading customers. It includes design reuse compliance checks such as STARC and OpenMORE to enforce consistent style throughout the design, ease the integration of multi-team and multi-vendor IP and promote design reuse.

The Methodology
Atrenta's SpyGlass solution methodology provides a structured, easy to use and a comprehensive method for solving RTL design issues, thereby ensuring high quality RTL with fewer but meaningful violations.

Provides methodology documentation and rule-sets as part of the product
Provides an infrastructure for rule selection and customization aligned with design milestones
Walks users through a series of recommended steps to ensure design compliance to HDL standards, coding style, synthesis, simulation, verification, connectivity finite-state machine, clock and reset issues
This step-by-step approach detects and fixes design bugs in alignment with design milestones, and ensures predictable design closure without any last minute surprises or a high volume of violations

Features & Benefits
Sophisticated static and dynamic analysis--identifies critical design issues at RTL
Industry-leading comprehensive clock, reset and clock domain crossing (CDC) analysis
A comprehensive set of electrical rules checks to ensure netlist integrity
Customizable framework to capture and automate company expertise
High performance and capacity to rapidly analyze complex, multimillion-gate designs
Integrated debug environment enables easy cross-probing among violation reports, schematic and RTL source
The most comprehensive knowledge base of design expertise and industry-standard best practices
Supports Verilog, VHDL, V2K, SystemVerilog and mixed-language designs

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