Synopsys-PrimeTime_StandAloneV2008.06 for Linux license keymake

PrimeTime® is a full-chip, gate-level static timing analysis (STA) tool for 100 million-gate designs. PrimeTime provides a comprehensive solution that combines static timing analysis, accurate RC delay calculation, advanced modeling, and timing sign-off in an easy-to-use product. PrimeTime’s performance enables multiple full-chip timing analysis runs of multimilliongate designs while exhaustively analyzing all critical paths. It is ideal for large, multi-frequency designs that combine synthesized logic, embedded memories, and microprocessor cores.
Key benefits:
1 Industry-leading performance and capacity–64-bit architecture allows full-chip timing analysis of 100-million gate designs; Incremental analysis reduces runtimes for minor design changes and improves productivity; Support for binary parasitics
2 Golden delay calculator–Built-in RC delay calculation uses parasitic information from SPEF, DSPF, and RSPF files; Widely adopted in flows worldwide
3 Advanced modeling–Interface Logic Models (ILMs) for hierarchical static timing analysis and sign-off; Extracted Timing Models (ETM) for cell-based reusable IP and physical synthesis design flows; ASIC vendor sign-off and foundry support

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