Mentor Graphics Corporation, (NASDAQ: MENT), the market and technology leader in printed circuit board (PCB) design solutions, announced the availability of the PADS I/O Designer(TM) product specifically targeted at its PADS(R) product user community. For designers implementing complex field-programmable gate arrays (FPGAs) on their PCBs, the I/O Designer(TM) product has a proven track record of decreasing design cycle time, improving performance, and lowering product costs. These same benefits are now available to the PADS product users at an aggressive entry price as the use of high density, high performance FPGAs increases across the spectrum of electronic products. For the first time the PADS I/O Designer product is being made available to the PADS community.

"Mentor Graphics has demonstrated exceptional productivity benefits in optimizing the FPGA-to-PCB integration process with I/O Designer," said Danny Biran, Altera's senior vice president of product and corporate marketing. "The introduction of I/O Designer for PADS will bring the benefits of cycle time reduction and lower PCB costs to a broader FPGA / PCB customer base. Altera's advanced FPGA technology, combined with I/O Designer for PADS, is a perfect solution for the PADS user to expand their mainstream FPGA usage."

"Providing an industry-leading integrated and concurrent FPGA / PCB design process has been a major benefit to our customers," said Henry Potts, vice president and general manager of Mentor Graphics' Systems Design Division. "Users of high-end FPGAs report time-to-market reduction and systems performance improvement of up to 50 percent, and reductions in PCB layer counts resulting in reduced product costs. With the continuing trend in electronic products of using even more high-end FPGAs, the impact of providing I/O Designer to our PADS users is significant."

The PADS I/O Designer Product
The PADS I/O Designer family provides for concurrent design of the FPGA and PCB by bridging these unique design flows and automating the various processes needed to implement today's high pin-count, high-speed FPGAs on PCBs. Starting with nothing or an early hardware design language (HDL) description or a top-level DxDesigner(TM) product, the FPGA-PCB interface is quickly defined with a variety of correct by construction, drag and drop PCB signal to FPGA pin assignment methods. The PADS I/O Designer product then synchronizes the interface across the FPGA and PCB flows through:

Automatic DxDesigner and schematic generation
Automatic generation & maintenance of required FPGA vendor files, HDL files, and synthesis constraint files
Optionally, the PADS I/O Designer product will import the PADS Layout physical design for FPGA vendor rules-driven pin swaps. When extended to PCB optimization, the PADS I/O Designer product leverages the PADS Layout physical design to drive PCB trace optimization through FPGA interface unraveling. Also available is functionality to optimize multiple FPGA interfaces simultaneously within a single PADS Layout physical design.

No comments: