Designers of today's SoCs must manage shrinking geometries, increasing design sizes, and growing complexity. As a result, the technical challenge has become how to account for the effects of interconnect across the entire chip—from the outset of the implementation cycle. Additonally, electronics makers need a design system that can deliver the highest quality of silicon (defined as timing, area, and power with wires) along with accurate verification, signal-integrity aware routing and the latest low-power design and yield capabilities, which are critical for advanced 65nm and 45 nm designs.

Cadence SoC Encounter system addresses these requirements within a system that combines RTL synthesis, silicon virtual prototyping, and automated floorplan synthesis, clock network synthesis, design for manufacturability and yield, mixed-signal support, and nanometer routing. Optimized to support 130nm to 45nm designs, it enables full-chip implementation in a single system. SoC Encounter allows engineers to synthesize to a flat virtual prototype implementation—including full-chip, routed wires—at the beginning of the design cycle. Engineers have an early, accurate view of whether the design will meet its targets and be physically realizable. They can then choose to either complete the final implementation or to revisit the RTL design phase. The SoC Encounter system also supports advanced timing closure and routing, as well as signoff analysis engines for final implementation.

SoC Encounter boosts the productivity of design teams, helping them to manage design complexity, and get products to market faster. The SoC Encounter system is available in L, XL, GXL offerings.

Key Benefits:
Combines RTL synthesis, silicon virtual prototype and full-chip implementation in a single, silicon-proven system to achieve timing closure on complex designs
Provides fast, accurate and flexible feasibility analysis—which combines an automated floorplan synthesis and ranking system that enables rapid exploration of the design space with handoff to the physical implementation flow—for a predictable path to design closure
Delivers huge productivity gains through a high-capacity, high-throughput and highly integrated solution that can handle 50M+ gate designs in 130nm process technologies or below
Supports multiple implementation styles with built-in fast power planning, relative floorplaning, and signal integrity analysis
Supports multiple methodologies for flip-chip implementation with automatic RDL routing and 45 degree support, thereby promoting the concurrent design of chip and package
Proivdes highly integrated and consistent process variation fixing with the SSTA solution (includes In-the-Die, Die-to-Die, and Random variation support, block-based and path-based modes, standardized statistical ECSM library models, and characterization support
Incorporates the latest yield and low-power design capabilities for advanced 65nm and 45nm designs

No comments: